1. Technical Field
The present invention relates to a semiconductor device with improved gate refresh characteristics and a method of fabricating the same.
2. Related Art
With the high integration degree of semiconductor devices, the size of an active region and a channel length of a transistor formed in the active region are reduced. As the channel length of a transistor is reduced, short channel effect or source/drain punch-through occurs, which negatively influences the electric field or electric potential in the channel of the transistor. For example, when a short channel effect is generated in an access transistor adapted to memory cells of dynamic random access memories (DRAMs), a threshold voltage of the DRAM cells is reduced and a leakage current increases, thereby degrading the refresh characteristics of DRAMs. Thus, in order to suppress the short channel effect, a method of increasing the gate channel length of the device formed on a substrate has been suggested. For example, even if the memory cells of a DRAM device are scaled down to a very small size, a transistor having a recessed channel retains fairly good refresh characteristics.
Hereinafter, a method of manufacturing a transistor having a recessed channel in the related art will be described. A source/drain region is formed by implanting impurities into a substrate. A mask opening a portion of the substrate in which a recessed channel is to be formed is formed and the exposed portion of the substrate is etched using the mask to form a trench in the substrate. Subsequently, a gate oxide layer is formed on an inner wall of the trench. At this time, the gate oxide layer includes a high dielectric (high-k) material layer such as a silicon oxide layer, a hafnium oxide layer and a hafnium silicon oxide layer. A gate conductive layer fills the trench. The gate conductive layer includes a stacking structure of polysilicon/metal or metal/polysilicon/metal, which has a lower resistance characteristic than polysilicon while having a property similar to polysilicon. The gate conductive layer is isotropically etched using a gate mask to form a gate electrode, thereby completing a transistor having the gate electrode and the source/drain.
Thus, as the integrity degree of the semiconductor device rapidly increases, in order to reduce a gate leakage current and power consumption, a high dielectric material layer is used as the gate oxide layer and a stacking structure, which includes a polysilicon layer on a metal layer, is formed on the high dielectric material layer as the gate conductive layer. However, when a transistor having a recessed channel is formed by the related art, due to low etch selectivity between the metal layer used as a gate conductive layer and the high dielectric material layer, when the high dielectric layer is etched to form the gate electrode, silicon substrate is removed.
On the other hand, as integrity of the semiconductor device increases, the thickness of the gate oxide layer is reduced to improve controllability of the gate. As a result, an electric field is concentrated at an area between the gates thus causing gate induced drain leakage (GIDL). That is, since an overlap between the gate and a junction region is increased by bridges between a word line and a bit line or between word lines, GIDL current is increased by direct tunneling between the gate electrode and the drain region. Such a GIDL current seriously degrades a semiconductor device, such as DRAM, having a recessed channel.